1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a synchronous semiconductor memory device having a wave pipelining control structure, and a method for outputting data using the same.
2. Description of the Related Art
In general, a synchronous semiconductor memory device differs from a conventional memory device in that data input and output operations are performed in synchronization with a memory system clock. In the synchronous semiconductor memory device, all input and output operations are normally synchronized with a rising edge of an external clock signal. Such operation reduces memory access time and allows a system designer to design a simple interface.
A conventional memory device performs a sensing operation after selecting a word line. It is impossible to select another word line during a precharge operation for the selected word line. However, a synchronous semiconductor memory device includes two or more memory array banks each having a separate row control circuit. There is no limitation as in the conventional DRAM between word lines located in different memory array banks. Word lines in different banks can be continuously accessed, thereby increasing the amount of accessible data and the speed of data access as compared with the conventional DRAM.
The synchronous semiconductor memory device is characterized by a "read latency" which represents the delay time until the first data is output. After the read latency, data is read out according to an internal data access clock, and is not dependent on a critical path within the memory device.
Generally, the synchronous semiconductor memory device adopts a multi-stage pipelining control structure as its data output structure. The multi-stage pipelining control structure includes data latches along a data path from the memory cell to a data output pad, and a transmission gate-type switch between latches. The switch is synchronized with a clock, and controlled by pulse signals.
However, the multi-stage pipelining control structure requires more data latching steps as a clock frequency increases and as the number of latching steps increases, the read latency increases.
A wave pipelining control structure is a data output control structure that minimizes such increase in read latency. In the wave pipelining control structure, a plurality of parallel latches are controlled by a control signal which is delayed in synchronization with a clock signal. The wave pipelining control structure does not increase the read latency even if the frequency of the clock signal increases.
FIG. 1 is a block diagram of a semiconductor memory device having a conventional wave pipelining control structure. During a read operation, data is read from a cell designated by an external address via a bit line BL and an input/output (I/O) line. The read data is amplified by a sense amplifier 101. A controller 103 detects a rising edge of an external clock signal to generate a control signal ODL0. A register 105 stores the signal amplified by the sense amplifier 101 under the control of the control signal ODL0.
According to the conventional wave pipelining control structure, a control signal ODL0 that controls the data of the first clock prevents the data from being stored in the register 105 and the control signal ODL0 is controlled by the controller 103 to delay only the first clock signal by a predetermined time.
However, the above-described conventional wave pipelining control structure suffers the following drawbacks. As the integration density of the memory device increases, the data output rate from a memory cell region becomes more sensitive to variations resulting from the manufacturing process. However, the data control signal ODL0 is generated in a periphery circuit portion such that its sensitivity to any fluctuations in manufacturing process conditions becomes relatively small. When implementing the conventional wave pipelining control structure, the control signal ODL0 is delayed by a predetermined time. If delay occurs on a data path due to variations resulting from the manufacturing process, the memory device malfunctions because before the accessed data reaches the register 105 on the data path, level transition of the control signal may occur, and block the input. In this case, even though the memory device is operating at a low frequency, since the control signal derived from the first clock is delayed by a predetermined time, the malfunction of the memory device persists.